Comparative study on the energy efficiency of logic gates based on single-electron transistor technology

The performance and the power consumption of single-electron transistor (SET) technology-based ultra-energy-efficient signal processing circuits are compared based on the SPICE model including non-ideal effects of the experimental data for the first time. In terms of ultra-energy-efficient logic circuits, the binary decision diagram (BDD) logic circuit is the most promising with a dissipated power of 0.29 nW at Vdd = 0.1 V and fin = 50 MHz among the static complementary metal-oxide-semiconductor (CMOS)-like SET logic, the dynamic SET/CMOS hybrid logic, cellular nonlinear network (CNN) and BDD. This result means that the transition of a paradigm substituting the current for the voltage as a state variable of a signal processing is strongly required in post-CMOS signal processing and ultra-energy-efficient applications. (Some figures in this article are in colour only in the electronic version)